The present invention relates generally to the manufacture of high performance VLSI semiconductor chips, and more particularly to a method of manufacturing a plurality of levels of interconnection metallurgy for personalizing such semiconductor chips.
A semiconductor chip comprises an array of devices whose contacts are interconnected by patterns of conductive wires. As the density of devices fabricated on a given chip increases, problems arise in providing interconnections between the various devices. In order to take full advantage of the device and circuit density on a given chip, it is necessary to make interconnections among the various devices and circuit elements in the chip in a high density manner. However, due to the level of integration of devices and circuits on a chip, interconnections can no longer be made by means of a single level network of conductive lines. Instead, it is necessary to provide at least two, and preferably three or more conductor interconnection levels, with each interconnection level separated by an insulating layer. Connections are made between these different interconnection pattern levels by means of via holes which are etched through the insulating layers separating these levels and which are filled with metal to form studs. These multiple levels of conductor wiring interconnection patterns, with the individual levels connected by conductor studs, operate to distribute signals among the circuits on the chip.
Prior art multilevel interconnect systems generally utilize a straight-forward approach of photoresist patterning and etching operations to construct successive layers of insulating material and conducting material (metal) to form a personalized interconnect system. However, because of process related design constraints inherently involved in this fabrication process, the multilevel interconnect systems which can be produced are greatly limited in their overall density of interconnections.
In particular, conductive interconnection lines for a given interconnection level and interlevel via studs currently are separately formed by means of metal evaporation through a liftoff stencil. Generally, spaced pedestals with overhangs are utilized to form the liftoff stencil. When metal is evaporated into the spaces between the various pedestals, the pedestal overhangs insure that the area directly below the overhangs remains free of metal. The evaporated layer is then immersed in a solvent which attacks the pedestal through the metal-free areas between the base of the pedestals and the evaporated metal to thereby effect the pedestal removal, while leaving the metal stud or line.
However, evaporated metal is very conformal. The conformal nature of this evaporation causes significant dips in the evaporated layer over the via holes due to the evaporated layer following the topography of the hole. The resulting lack of planarity for the evaporated metal layer causes tolerance problems in later processing steps because the tops of the interconnection lines and the via studs are now at different levels. This tolerance problem is exaccerbated as the number of interconnection layers increases. Additionally, if the via holes have sharp edges, then weak points subject to breakage occur in the conformal layer at these edges. To solve this problem, the via hole edges must be rounded. However, such via edge rounding increases the area of the via hole at the surface of the insulating layer in which it is disposed. The resulting via-hole area-increase causes a significant decrease in the possible conductor pattern density of the interconnection level disposed over this insulating layer.
An additional problem with this process is that there is no known method for evaporating metal with the sufficiently small angle of incidence that is necessary to effect liftoff from substrate layers greater than 12 cm in diameter. The use of evaporation techniques on such large diameter substrates results in metal deposits under the pedestal overhangs, thereby preventing pedestal removal and causing short circuits.
A further problem with the evaporated metal technique is that it is difficult to properly form an insulating layer in high aspect ratio (height/width ratio) spaces between adjacent studs or lines after the stencil pedestal has been removed. As the space between adjacent 2-3 micron high studs or lines drops below 2 microns, this insulation problem becomes especially acute.
Sputtering is an alternative technique for depositing a conductive layer. However, sputtering is not indicated for forming patterns through a liftoff stencil as described above because the sputtered metal coats and adheres to the sidewalls of the pedestal and the pedestal overhang used to form the studs and interconnection lines. The adherence of the metal to the sidewalls of the pedestals below the pedestal overhang prevents chemical solvents from reaching the pedestal to effect its removal. Sputtering, as previously practiced, is also not indicated for filling deep, vertical walled vias because of its tendency to adhere and accumulate to the via sidewalls. Accordingly, as the metal coating increases in thickness on these sidewalls, the metal coatings on opposing overhangs join together, leaving an unfilled void in the space between the pedestals.
Although sputtering is not indicated for filling via holes, it may be possible to use sputtering to form the interconnection level lines. Such a technique would comprise the sputtering of a layer of metal over a given insulation layer, followed by the removal of selected portions of the sputtered layer to define various metal lines. This metal removal can be effected via either a wet etch process, or by means of a reactive ion etching process. However, the wet etch process is isotropic in nature, and thus cannot be used for dense pattern applications. RIE however, is anisotropic in nature and can be used to form dense conductor patterns if appropriate RIE barriers are first deposited. But, the standard Cl.sub.2 gas used in metal RIE is corrosive to the underlying device. Moreover, the RIE etch rate is pattern dependent due to certain RIE by-products formed during the etching process. Thus, close line patterns etch at a different rate than isolated lines on a given chip. Additionally, the standard RIE over-etch required due to the various tolerances involved creates mouseholes in any exposed via studs underlying the overetched region. Finally, there are currently no commercially available RIE etches suitable for etching Al-Cu alloys with more than 2% Cu by weight; the preferred alloys for forming interconnections.
The invention as claimed is intended to remedy the above-described problems in forming dense interconnection patterns.
The advantage offered by the present invention is that a given level of interconnection conductors and the interlevel via studs set therebelow can be formed simultaneously to very tight tolerances. The process used in this formation avoids the planarity problems, the angle of incidence requirements, the rounded via edge requirements, and the stud insulator problems of standard evaporation and liftoff techniques. Likewise, the present process avoids the void formation problem, the pedestal removal problem, and the subtractive etching problem attendant to the use of standard sputtering techniques. This process provides interconnection level planarity and is also extendable to substrates larger than 12 cm in diameter. Additionally, this process can be used to form and fill via holes with high aspect ratios of 1.5 to 1 or greater. Accordingly, this process is especially suited for high density interconnection patterns.